For any design, let it be Analog or digital, timing is one of the specification that has to be met.
Timing arcs like Combinational delay, setup & hold are measured for a block generally by simulating them, i.e stimulate the block with dynamic signal and measure the output (Dynamic Timing Analysis). This would get cumbersome if the block is huge like SOC, because
1. it involves manual identification of combinational path, Data path, Clock Path, Clock gating path & Asynchronous path and measure corresponding timings between the Pin & Related Pin for each of the path.
2. Simulating the huge block will be a burden and time consuming for simulator.
3. Requires more memory for simulation.
4. Time to market factor will be affected tremendously.
How do we automate the identifying and measuring the timing arcs for Large blocks?
Automation industry has employed conventional Module technique, module a top SOC into simpler blocks whose timings are very easy to interpret and measure. Yes, our instinct says Gates are that lower modules. Once the timings for Gates are measured, we integrate those timings in the top level. Integration of timings of Gates are Automated, it requires each lower module's timing information in a particular syntax, this gave rise to library generation or Characterization.
And delay modle for the routings between modules are taken from Unified routing modle.
How does lower modules behave with different load?
We know that timing measurements change with change in loads. How do we account for that in the library generation? .lib files incorporate input capacitance for each input pin, and timing arcs are measured by sweeping the output load from lower to upper defined value (it's usually decided with smallest & largest input load that can possibly connect).
How modules are integrated and timings are measured in the top level ?
Now we know that .lib files are written for modules. It has pin information, input capacitance for all input pins, all timing arcs between Pin & Related Pin. Netlist gives the connectivity information between these modules in the top level. So, a netlist (preferred is verilog) with stop level to Gates should be generated. .lib files are used as look-up table and connectivity is established using netlist generated. Algorithms are written now to dump timing information for the Top block.
Tools like Prime Time of Synopsys and Encounter timing system of Cadence are preferred in industry for this.
How should analog blocks be handled?
Unfortunately since Analog blocks are comprised of complex different topology with transistors, it has to be treated just like Gates, where manual computation of timings has to be done. However there are automation emerging for bringing down the manual computation in these cases also like Liberate/MX/AMS from Cadence.
