CMOS chips are susceptible to the ESD strikes. EDS strikes
produce huge current through the pins that can damage the gate oxide of the transistors,
this will affect the functionality of the chip.
It’s essential to protect the chips form the ESD strikes to
make it durable. Firstly, the fundamental idea here is to create conduit
to the huge currents of ESD strikes. The conduit circuit should not be the
factor for the leakage power in normal case. ESD strikes can happen in many ways, these
strikes are modeled for the testing of the ESD cells. You can refer to the
below mentioned link to know about different ESD models:
Now
let’s have a look at the circuit given in the right.
When the
signal is varied from minus infinity to plus infinity in voltage, can you plot
the current
through the MOSFET versus the
signal voltage?
Well, if you were thinking the NMOS will be off all the time, you are
wrong! Have a look at the Cross-sectional view of the same circuit. And focus on the diode formed
between the drain and the substrate.
With the graph of IB versus VDB variation. This above structure can be considered for ESD protection circuit design.
In reality MOS SNAPBACK will occur. As voltage VD increases, the drain to body
leakage will increase. This leakage current passing through P+ will introduce
voltage drop across RPSUB. At critical VD=Vt1, VPSUB is huge enough to turn the
NPN transistor on. As transistor turns on most of the current directs to INPN (shown
in the figure) bringing down the voltage VPSUB snapping the voltage VD back to holding
voltage VH. VD and INPN increases and breaks-down beyond a point.
Being over precaution below mentioned circuit is generally employed for ESD protection.
As length of transistors getting reduced with the node technology. If this structure is used to protect the gate of a MOSFET, the Vt1 will be equal to VGB for the thin oxide MOSFET making it less reliable to protect the gates of MOSFET. It is also found that thin oxide MOSFET breaks-down as soon as it enters snapback region. However, thick oxide MOS can be in snapback region for some time before breakdown .
